The SLC is a very affordable single or dual clock 7 GHz synthesiser. It exhibits outstanding phase noise and jitter performance in a very small package. With -170 dBc/Hz phase noise floor at 10 MHz, the SLC is the lowest phase noise compact clock synthesiser of the industry. It can help the customer challenge tomorrow's requirements for high speed, high bandwidth Software Defined Radio applications (SDR) and low phase noise PLL and DDS synthesis.
Its high power output is ideal to drive mixers' LO inputs or high-speed digital clocks. It’s very low jitter profile makes ADC and DAC testing more accurate. This source is often cleaner than a crystal oscillator and can offer a high SNR, up to 135dB. USB, SPI or LAN control helps to seamlessly integrate this tool in test projects or clock distribution architecture. Both synthesisers can be controlled completely independently and do not share any common reference frequencies. However, when coherent signals are required, they can be locked to each other with the help of their 10 MHz reference signals.
Optional ultra-low phase noise OCXO allows the synthesisers to reach their best specification and if this is not enough, the external 10 MHz reference input will extends its long-term frequency stability (Allan variance) to one of atomic clocks.